Code conversion device



Dec. 29, 1964 L. w. sTowE CODE CONVERSION DEVICE:

Filed March 2l, 1962 Ow @E QON A TTORNE Y United States Patent O 3,163,859 CUBE CONVERSIGN DEVICE Lloyd W. Stowe, Broomall, Pa., assigner to Sperry Rand Corporation, New York, NY., a corporation of Delaware rned Mar. 2r, 1962, ser. No. 181,279 s Claims. (er. 34e- 347) This invention relates to a device for translating information or data in one system or notation into dat-a in a second or further system of notation and more particularly to a device for converting a single unit of data or information into successive units of data or information in different scales of notation at consecutive time periods.

Due to the wide acceptance of computing devices .in many fields of science and industry, it is necessary to construct calculating devices to meet a wide variety of needs. These needs may be expressed as different requirements for storage, operating speed, size of the word to be handled in the calculation, and other such similar factors. To design components for each of these syst-ems is expensive and requires much repetition of the same basic design techniques. It is much simpler to permit the use of a single element in a number of computing devices makin-g proper allowance for the differences in physical characteristic which exists between the element and fthe system in which it is to be employed, It is thus possible for example to employ a single magnetic core memory matrix, which has sixteen planes and is capable of supplying a sixteen bit binary Word in a device requiring 48 binary bits, simply by the system of addressing the same memory matrix three successive times. The only requirement which would be placed upon such a system is that :the three addresses which are used to select the three 16 bit binarywords are unique, In other words that each address Will select a portion of the matrix which is not addressable by the other two addresses.

It is therefore an object of this invention to provide a translating device which may accept a first unit of information or data in a first system of notation and translate it -to further units of information or data in further systems of notation.

It is a further object of this invention to provide a translating device whereby an original unit of information or data may be converted into successive discrete units of information or data in different systems of notation at successive time periods.

lt is another object of this invention to provide a translating device which may convert a number in coded decimal form into a further series of numbers each of which is in another form.

Briefly stated, the invention (in its preferred form) consists of employing a register device capable of storing three computer digits in coded decimal form and translating these digits by means of a logical gate matrix into a plurality of unique effective addresses during separate time periods as defined by individual start pulses. in operation the register is loaded with the 12 bits of the control address, during la first start time, which bits are employed a first effective address composed of l2 binary digits which may be employed to address the actual matrix. During a second time period as established by a second start pulse, the effective address which has been employed during first time pulse is modified to provide a second effective address which will be employed during `this time period to further address the matrix. And finally, during the time of a third start pulse the effective address generated as a result of the second pulse is lagain modified to provide a third effective address to :address the memory a third time. In this. manner it is possible to employ the matrix which has only 16 planes and will l in that position, the bits of the second bit position asr4 pro-vide 16 binary bits to provide the required 48 bits of the using device. This procedure may be employed for read in or read out purposes from the matrix.

Other `objects and features of the invention will be pointed out in the following description and claims and illustrated in the accompanying drawings, which disclose, by Way of example, the principle of theinvention, and the best mode which has been contemplated for carrying it out.

In the drawings:

FlGURE 1 illustrates a device constructed in accordance with the basic concept of the invention;

FGURE 2 shows a timing control device which may be employed with the device of FIGURE l;

FIGURE 3 illustrates a logical And gate;

FGURE 4 illustrates a logical Or gate.

Referring now to FIGURE l there is shown a translating device constructed in accordance with this invention. The input information or control address is placed into a register designated as the memory address register or MAR, composed of 12 flipdiops designated CH5, CH4, CIZ, CH1, CT5, GT4, CTZ, CTl, CU5, CU4, CU2 and CUl. These 12 ip-ops represen-t the three coded decimal digits of the control address. The hip-flops CU5, CU4, CU2, Iand CUl represent the most significant bit, the third significant bit, the second significant bit and the least significant bit of the units order of the control address. Similarly, the flip-flops CT5, GT4, GT2, and CTl represent the most signicant bit, third significant bit, second significant bit and least significant bit of the tens order of the control address. The flipdiops CH5, CH4, CH2, and CHI represent respectively the most significant bit, the third significant bit, the second significant bit and the least significant bit of the hundreds order of the control address. of :the MAR in a coded decimal form employing the values of 5, 4, 2 'and l. The information is stored into these flip-flops according to the following table, with columnar Weights as indicated:

Table I The control address is stored into the flip-flops- BiQninai-y Codo Decimal Digit MSB LSB Simplification, in order to achieve uniqueness may be predicated upon the following analysis of the digits (numeric) which can exist as the control address digits. Considering the numerics 0 through 9, the digits 0 through 4 are symmetrical with the digits 5 through 9 with the exception that a zero occupies the most signicantbit position of the digits 0 through 4 Whereas a one occupies the most significant bit position of the digits 5 through 9. Thus the same circuitry may be employed for all digits 0 through 9 providing the most significant bit position is properly accounted for. Next, if the third bit position is considered, it can be seen that it a one exists Table IIa-Continued A. CONTROLLING ADDRESSES significant bit position must both be posiwould U U U U mv.. 1100011000110001100011000110 W 00110001100011000110 mw U00110001100011000110 mw 00110 m 0010000100001000010000100001 U4 00001000010000100001 U4 `00001000010000100001 u. 0000.1 Hrw 0000000000000000000000000000 Ua 00000000000000000000 Ua ,00000000000000000000 .Ua 00000 S S T1.. 0000111100000111110000011111 @nu .m1 T. 00000000000000000000 w mm. 00000111110000011111 my T1.. 00000 2 1111111100000000001111111111 R S 2 00000000000000000000 R 2 00000000001111111111 E 1 2 00000 T D m T D 1 T R T4 T t 1 0000000000000000000000000000 D 4 4 11111111111111111111 D HD. 4 00000000000000000000 D d 4 11111 T A n T A m T D m T .1 5 0000000000000000000000000000 G t .n 00000000000000000000 G f. 5 00000000000000000000 A 14 5 00000 T N w T N 0 T G u T 1 S I e 0 H1 0000000011111111111111111111 m m E. 00000111110000011111 m M 1... 00000000000000000000 m H. 00000 p m L n O S O e e m 1111111111111111111111111111 R W. 00000000001111111111 R DM vr. 00000000000000000000 m vm 00000 T W T .1 R nu 4 0000000000000000000000000000 N M 4 00000000000000000000 N 4 11111111111111111111 T 4 11111 H O .t H O H N H C m C O La 0000000000000000000000000000 1 00000000000000000000 l 00000000000000000000 C E 1 B C III :I: D 2 3 L2 3 4.0 L2 8 4 O L O LSMLOZLOZMmHhLZL 0. 4 0 12 3 4 mm2 wwwwwmm MMMMOMMMMMMMmn/ MMMWMM m m 0 Ru 0 0 :d 0 0 D O D 0 5 5 1 1 2 3 3 4 4 5 5 6 6 7. 7 n .la 1M n n d 1 nw 0101001010010100101001010010100101001010010100101001 O .1 a T n e t S 4 .l m t 1 e C 6 .1 ed O T .D n 4 .t t 1 h h a H D S a .1 w nw m O m m h L m +L man y e f n L a m D M W 0011000110001100011000110001100011000110001100011000 f r pn S o umm Cm S .mmdd L a p Sd n S M 11am V. Us 0000100001000010000100001000010000100001000010000100 i nu d .Hentet e eH .D W 0 y L.1 O 1 p.n S a 444.4 d10. nu m S m S m a S M VIM C 0000000000000000000000000000000000000000000000000000 1 U1 f. i a 1 S n O .1 n S O n.1 e O d .H1111 0123 a wf m Mo muy m n .lmnm m m 4444 wm TJ. 0000011111000001111100000111110000011111000001111100 D O L O 0 y G .1 0.1 d.1 1 S d i. WO ermhefuuu 6.4.1.... .IHM Dn M4MM En 2 .U w a Ch Svm M L .b e S Cm.1.1 0M23 R .w T 0000000000111111111100000000001111111111000000000011 6.1 L.1 n h 6.1 O e B nw ...h .DS S..s dOCHD. 1u diff @4mm Ds T m.. rm m 3.0m@ C t L g e a 0123 a D 0H T. 0000000000000000000000000000000000000000000000000000 1 .1 ...H U 444A.. HAT4 5 S10, L a 0 .GVlLcL m .J m g T.. e w t T 0000000000000000000000000000000000000000000000000000 ut dXSacOa h. r .15.161 w 61o 1 D e 1.4L C d pe D Od b 0 0 1 1. 1 a a. d 1S.. e1 p0 n W S um a 1D L 0000000000000000000011111111111111111111000000000000 Vc u mdovusadiwnn WOT MLn H. he faP o esria eon 0i 1d ytm a R m 0000000000000000000000000000000000000000111111111111 1 c1 O f. S 1D.1 .1 e i e I r n e e e e we T b y 1.1 0 L U e a 0 1 m 51m a C O Wh h.. Wo w new m WHW@ W W 0000000000000000000000000000000000000000000000000000 L S r 0 S m ma @md .lu s nih s 1 A C i m e ma u @0.10.1 d t .1 6T m MHMM 0000000000000000000000000000000000000000000000000000 1 1111 O .IODdH .1 nOScLdSM ddr L nrnr A netba.1na AaSe Odea.ddf Own/ 3 mmmmrnw cnmnaTDaae 1111 asof eiem oe ole 11uV nacembm mmmnmmwq .11 S.1.1n CnS.Sd.Wv.$d.1a 1.1m MMMM 1VCV ...1S1DOS .1 n nn 0000 Lef-.n yar .leonadOOaW 00u 1m arouter.. hrp p OCCC swnTHanddtwgtCl d mmm@ 65.1 00013 d.1.1n.1 .le :ffn 131D r1.1CO1pabT11D bBOOa l.

well as the least zero. This is true because to allow a bit in either tion when the third bit position contains a one The control address set out above in the Tables il and Ila are arranged to have zeros in the most signiiicant bit positions of the digits in the units, tens and hundreds orders for illustrative purposes only. These most signiiicant digits may be any combination of ones and zeros, from all zeros, as shown, to all ones. The rules for the formation of the effective addresses will be the same for all the remaining bit positions regardless of the most significant bit value. The Value of the most significant bit of the control address will be used directly, and the equivalent bit of the ettective address wili always be the same as the bit or" the control address. An original controlling address is set up in the flip-hops of the MAR and will remain there unchanged through the entire operation of the device. It Will be the outputs of these particular flipiops plus certain other special signals on the eiiective lines, designated lines EH5, 15H4, EH@ BH1, ET5, ET4, Erl-2, ETl, EU5 EUL, EUZ, and EUl iliCl Will adect the actual selection and Will be considered the effective addresses for selection purposes. in order to continue the uniqueness which has been shown by the control addresses in Table ll it is necessary to alter the control addresses according to particular patterns depen ing upon Whether the control addresses fall into groups A, B, C or D. The manner of alteration will be set forth below.

The iiip-fiops of the MAR register are Well known in the art and are of the type which when storing a zero or in the reset condition, provides a low output on the zero line and a high output on the one line whereas When it is storing a one or in the set condition, the Zero line is high and the one line is low. The one output of dip-flop CUI is connected by a line i@ to the right input terminal of an And gate d, the left input of which is supplied by the zero output of flip-dop CT4 over line i2. 'Bhe output of the And gate e is supplied over a line 14 to the Or gate lo. Flip-flop CU2 has its one line connected via line 18 to one terminal of the Or circuit 20 and further connects to one input of the And circuit 4 via the line Z2. The one terminal of dip-flop CU4 is connected via line 2li to an input vof the-Or circuit 26 and is further connected via line 28 to the input o And circuit S. The one terminal of the hip-flop CU5 `is connected directly to the Or circuit 3i? by the line 31, whereas the one line of the iiip-fiop CT1 is connected directly to an Or circuit 32 by a line 3d. The one output lof flip-Hop CTZ is connected directly to an Or circuit 36 via a line 38. rThe one output of dip-flop CT.; is connected via lineV d@ to an input of the And circu-it 4, to an input of the And circuit 3 to an input of the r circuit 26 and finally to an input of the And circuit as set forth above. The output 1 of flip-Hop CT5 is connected directly to the Or circuit 42 via line 4d. The output of flip-flop CHI, that is the one output, is supplied via a line d6 to an input of the Or7 gate 48, Whereasthe one output of flip-flop CH2 is connected via line Sti to the Or circuit 52. The one output of fiip-op Cieli -is connected via line 51tto one input of an Or circuit 56 the other input of which is supplied by a B pulse. Further the one output terminal of dipfiop CH4 is ,also connected to an input of the And circuit 2 which receives as its other inputa further B pulse, and to the And circuit i which receives as its other input an A pulse. The output of the And circuit 2 is connected to a further input of the Or circuit S2, Whereas the output of the And circuit i is connected by line 47 to the input of Or circuit The one output of dip-flop CH5 is connected via a iine StB to an Or circuit et).

Referring briey -to FIGURE 3 the manner of construction and operation of the And circuits of FIGURE l will he described. The And circuit or FIGURE 3 is composed of a first diode 1G@ and a second diode itil connected with their cathodes commoned to a resistor and negative supply. Input voltages are applied at the terminals designated X and Y to the plates of the respective diodes iti@ and M2, the output being taken from the terminal designated Z. in operation if negative pulses are applied to both the terminals X and Y a negative pulse will he produced at the output of the terminal Z. However, should a positive pulse appear at either or the inputs X or Y then the output at Z Will be positive. Or, stated another Way, if the inputs at X and Y are low then the output at terminal Z is also low Whereas ii the input to either of the terminals X or Y should be high the output at Z is also high. The terms high and positive or loW and negative will be used interchangeably and should be understood as such.

Referring now to FIGURE 4, the manner of construction and operation of the nega-tive Or circuits employed in FlGURE 1 are described. The gate is constructed using two diodes designated 2MP and 2M arranged to have their plates commoned via a resistor to a positive source. Pulses are applied to their bases via terminals P and Q or the two diodes 2d@ and 2M respectively, the output being taken from the terminal designated R. The gate operates to provide a negative or low output at the terminal R upon the occurrence of a single negative pulse or low pulse on either `of the Iterminals P or Q to the diodes 209 and itil respectively. The exact manner of operation of these two diodes is not set forth in that they are considered to be Well known in the art,

Referring again to FIGURE l, it is assumed that a con trol yaddress having a conguration designated under the A grouping of Table Il has been set into the register.

. During the irst time period outputs will be available at the respective Or circuits of the three sections of the register Eil, BH2, BH1, E17-F4, ETg, ETI EU4, EUZ, and EU1, depending upon the settings of the respective fiipiiops of the register MAR. it should be remembered that ilipdiops CUS, CT5 and CH5 will be set to zero (in this example) and the outputs on lines EUS, ET5 and EH5 Will accordingly be high. An inspection of Table Ila, containing the same information as Table II but in fully expanded coded decimal form, indicates the following: The flip-flops 'CT-I5, CT5, and CU5 are not set. Further, the flip-flops CH4 and CT are also not set for an A group address. This results in the outputs of the dip-flops GT4 and CH@ providing a lovI output on their zero lines and a high output on their one lines. The eiiect of the low output on the line 12 of the flip-flop GT4 is to enable or alert the And gate 6 for operation. The high output on the line d@ from the one output terminal of flip-flop GT4 produces a disabling or inhibit effect upon the And gates 3 and i as Well as the And gate 5. It should be remembered from the discussion of the operation of the And gate of FIGURE 3 that if a 10W or enabling pulse is placed upon one input the gate will be made operative upon the introduction of a further lovv to the additional terminal of the gate whereas if a high has heen placed upon the gate the subsequent application oi a low to the other terminal will be ineiiective to cause the gate to conduct and in effect the application of this high acts as an inhibiting or disabling pulse. The one or high output of iip-flop CH4 on the linet will act to disable the Andf gates ll and 2, and apply a single high input to the Or circuits 56 and o2. The result of this manner of operation is to produce an effective address dur-ing the rst time period which is the same as the controlling address for digits within the group designated A of Table 1I. For example, if the register were storing the value O04 the output of Or gate 26 to line EU4 would be low, Whereas the output of all the other Or circuits would be high, thereby causing an effective selection of the matrix address 4. It should be remembered that all selection and actuating purposes are served by the use of low pulses Whereas the highs serve merely as inhibit pulses for gating purposes. During a second time period the address stored in the memory address register MAR has its `output effect modified. It should be recalled that the contents of the memory address register (MAR) are not altered during the three time periods to generate the further unique addresses but rather than the output effects by means of the various gates are altered according to the time period invoived. To effect the selection of a second address when the value stored in MAR is within the group A of Table if, an A pulse is applied to the Or gate 62 during the entire period of selection of the second address so as to provide an BT4 signal of one regardless of the actual value of the control address stored in MAR. Thus the second effective address will be the same as the control address except that there will be a one present at the output BT4 for all control addresses in group A despite the fact that no original control address in group A could contain a pulse in the GT4 position. The A pulse applied to And gate 1 will be ineffective to produce an output because the second input to And gate 1 supplied by the one output terminal of flip-Hop GH4 will be high during any group A control address and inhibits gate l.

During the third time period the address stored in the MAR has its output effect modified a second time to produce the third unique effective address. This address is created from the control address by causing a one to appear at the BH4 line even though no input pulse can be present (in this example) in the GH4 fiipfflop. This modiiication results from the introduction of a B pulse to the Or gate 56 during this time period. The B pulse applied to And gate 2 is ineffective to produce an output due to the fact that the one output of fiip-op GH4 is always high for a control address in group A. Thus the effective address during this third time period will be the original control address plus a one inserted at line BH4 regardless of the other values stored in MAR.

Assuming now that a controlling address lying within the group B of Table II had originally been inserted into the memory address register MAR, the following effective addresses would be generated during the successive time periods. The B group addresses always having a one in the GT4 position will result in the dip-flop GT4 producing a low output on its one terminal which will have the effect of alerting the And circuits 3, i and 5 as well as presenting a constant low output condition to the Or circuits 20 and 26 thus providing a constant low output on lines BU4 and BU2. The high output on the zero line 12 flip-flop (GT4) will cause the And gate 6 to be disabled. It should be noted that the flip-flops GTI and GT2 when storing any address within the B group will always be in the Zero condition causing a high output to be available on the one lines of both of these flip-Hops.

Further, since the flip-flop GH4 will store a Zero during all of the address conditions (now being discussed) it also provides a high output on its one line to the And circuits 1 and 2 as well as the Or circuit 56. The effect of the high on the Zero line 12 of dip-flop GT4 to the And gate 6 will result in its inability to produce an output in response to the condition of the fiip-flop CUI. It will be appreciated if And gate 6 fails to produce an output the Or circuit 16 which is driven by this gate may not produce an BUI signal. However an BUI signal will be produced when a one is stored in the fiip-flops GU4 and GT4 as a result of the application of pulses to the And gate which also may supply the Or circuit 16 providing an output on line BUI. Asa result of this arrangement the following effective address is available during the first time period if a Value in the B group is established in the register MAR:

The output on line BUI will follow the setting of the flip-Hop GU4, the outputs of BU4 and BU2 will be one regardless of the settings of the respective liip-fiops GU4 and CU2, the output of BU5 will continually be zero for the operation. The output line BTI will follow the setting of the flip-flop CUI while the output BT2 will follow the setting of fiip-fiop CU2, the outputs BT4 and BT5 being zero. The output on the line BHI will be in accordance with the setting of flip-flop GHI and BH2 will follow that of CH2. The output lines BH4 and BH5 will remain Zero I for this example.

ln order to produce the second effective address during a second time period with a word originally in the group B of Table H the effective address generated during the iirst time period will be modified by inserting a pulse on the output selection line BT4. This `obtains because the A pulse is introduced to input of Or gate 652 during the second time period. Hence, a second effective address results which is the same as the first effective address with the exception that a one will appear on the BT4 line regardless of the content of the MAR. The A pulse at And gate ll does not effect the selection line BHI due to the fact flip-flop GH4 is always in a zero or reset condition for any group B controlling address.

The third effective address is generated from the first effective address by the insertion of a B pulse to the Or gate 56 causing a one to appear on the BH4 line regardless of the content of the liip-fiop CH4. The B pulse applied to And gate 2 is ineffective due to the fact that Hip-flop GH4 is always zero for an address of group B. An example of the manner of operation of the device to produce an effective address for an original B group conf trolling address (see Table II) is given below:

lf the original address stored in the MAR was 4,0 (i.e., 040) then the iiip-fiops therein would be set in the following manner, GHII, GH4, CH2 and GHI would all be set to Zero. (ST5, GT2 and GTI would each be set to zero whereas GT4 would be set to one. The flip-flops C5`, GU4, CU2 and GUI all store a zero. The outputs that will be produced on the output lines of the connector will be as follows: BUI and BU5 will remain zero, BU4 and BU2 will take the one configuration, the output lines BT5, BT4, BT2 and BTI will all be in the Zero form, as will be the lines BH5, BH4, BH2 and BHI. During the second time period the same effective address pattern will be shown with the addition of a pulse corresponding to the BT4 output line produced in response to the pulse applied to buffer 62. Further, during the third time period the configuration will be the same as the original effective address pattern with the exception that there will now be a pulse present on the BH4 line produced in response to the B pulse applied to buffer 56.

The manner of operation of the device with an address lying in the C group of Table II will now be set forth. The effective address signals which result during the first time period, from the control address in group C, will cause address signals to be generated having the following values: The outputs on lines BU5, BU4, BU2 and BUI will be the same as that stored in the respective flip-flops GU5, GU4, CU2 and GUI. Further, the outputs on the lines BT5, BT2 and BTI will also be similar to that stored in their respective flip-Hops GT5, GT2 and GTI. The one exception will be that the output on the line BT4 will be one regardless of the setting of the respective flip-fiop GT4. Position BH4, will be one due to the setting of its respective flip-Hop GH4 which is always one for a group G control address. The outputs on BH2 and BHI will similarly be zero due to the setting of their respective Hip-flops CH2 and GHI which are zero for a group G control address. Further the output of the flip-flop GH5 will cause a Zero output on the line BH5 through this entire operation.

The effective address generated during the second start pulse period is the same as the effective address which has been generated in the first time period with the addition of an output pulse on the lowest significant bit of the hundreds digit or the line BHI regardless of its actual setting. This is caused by the application of the A pulse during the second time period continually being gated through to the Or circuit d8 through the gate 1 due to the fact that GH4 is always in its one condition providing ka low pulse over line 54 to the And gate 1 at any time that a group G controlling address is present. The A pulse to Or gate 62 does not effect the result generated 9 because a one is always supplied to line B111 by flip-dop CH1 for any group C control address.

The third eiiective address during the starting pulse period 3 is the effective address generated during the first time period with a bit added to the second significant position of the hundreds digit or the BH2 position due to the fact that a B pulse generated during the third start pulse period is applied to the And gate 2 at the same time the one output of CH4 is applied to the same gate, As stated l@ is one throughout all group D control address also accounts for the B pulse being ineffective to change the value on line BH1.

They operation as set forth above is summarized by means of the Tables Illa to d. At the top of each table is indicated the condition of certain flip-flops not part of the particular group being considered, but which affect the result. The three columns under the heading MAR indicate the original control address digit placed in these above the 011e Output of the CE1 ip-ep is always 10W 10 particular flip-flops. The nine columns under the headduring a group C controlling address. he B pulse apings 1, 2 and 3 indicate the outputs on the selection lines plied to l[he Or gate S6 does not effect the eutpur 011 due to the effective addresses generated during the three line BH4 because a one is continually applied by flipstart pulse periods. It should be remembered that the efflop CH4 for a group C address. fective outputs of lines 4, 2 and 1 will be the same regard- Lastly the effective addresses being generated from less of the value of the 5 line or the value stored in the group D controlling address of Table H are set forth. 5I `flip-11013.

The group D controlling address will develop effective ad- Table Illa dress patterns which are mainly determined by the one [011:1]

stored in the iiip-iiop GT4 and the one bit stored in the iipfiop CH4. The effective address which is developed 20 MAR 1 2 3 from the controlling address will first take on a pattern ofthe following sort: The lines BUg'and BU2 will be one C11,1 CU2 C111 11111 E112 EU, 11111 1111:2 E111 E111 E112 11111 regardless of 'the settings of the respective ilip-iops CU4 and CU2 whereas the output of BU1 will follow the con- 0 11 0 0 0 0 0 0 0 0 0 0 tents of the iiip-flop CU4 rather than its respective hip-flop g5 g Q g (l) g (l) g (11' CU1. The output of the line BUB follows CT5 and in 0 1 1 0 1 1 0 1 1 0 1 1 this example is Zero. The output of line BI`1 will follow 1 0 0 1 0 0 1 0 0 1 0 0 the output of the iiip-fiop CU1 rather than its respective flip-dop CT1 in the present example and in a similar nian- T able [11b ner the output of line BTZ will follow the output of liip- [CTFH flop CU2. The output of ETL,g will remain one through the entire operation whereas the output of ET5 will re- MAR 1 2 3 main zero in this example. The outputs of lines BH5,

BH2 and BH1 will remain zero during a group D control- @U1 CU2 (1111 11114 E112 E11, 11114 11112 EU1 EU4 E112 EUl ling address whereas the line BH4 will remain one because 35 of the presence of a one in CH@g for all group D addresses. 0 0 0 1 1 0 1 1 0 1 1 0 During the second time period the effective address de- (.1 (11 (1) 1 1 g 1 1 0 1 0 veloped during the first time period is altered to include 0 1 1 1 1 0 1 1 g 1 i g a digit in the lowest significant bit position of the hun- 1 0 0 1 1 1 1 1 1 1 1 1 dreds digit by having a bit forced through the Or circuit 40 Table IIIc [OEM CU1and CU1=0] MAR 1 2 a CT1 GT2 GT1 E'li ETZ ET1 ETl ET2 ET1 ETi ET2 ET1 o 0 0 o 0 0 1 0 0 o o o o 0 1 0 o 1 1 o 1 0 0 1 0 1 o o 1 0 1 1 0 o 1 o 1 0 0 o 1 0 1 1 0 0 1 0 ir CU1=1 1 0 0 o 1 o 1 1 0 0 1 0 irCUi=1 1 0 0 0 1 1 1 1 1 o 1 1 ifCUf and CU2 are equal to 1 48 to line BH1 as a result of the A pulse which is available Table Illd only during the second time period and the pulse available on the output of the CH4 flip-flop which remains set MAR 1 2 3 to the one condition during any group D control address. The continuous one output prevents the application ofthe CE1 CH2 GH, 13H4 BH2 11H1 EH; BH2 E111 Eni 11H2 EH, other A pulse to Or gate 62 from affecting the result.

During the third time period a pulse formation similar o o o o o o o o o 1 o o to that for the rst eiective address is developed with the g (l) g (1 (l) (D) (11 1 (1) mere exception that a bit is now available in the second 0 1 1 O 1 1 0 1 1 1 1 1 bit position of the hundreds digit or the output of line l o O l .o o l 0 l 1 1 0 BH2 as a result of theB digit being applied to the And 1 0 D circuit 2 only during the third time period; thek other in- 1 0 n 1 i g i i i (i put to said And circuit Z being provided by the one out- (l) i 1 1 1 i put of ip-f'lop CH4 which is continually on during a 7V 1 0 0 1 0 1 1 1 0 group D controlling address. The fact that dip-flop CH1 Referring now to FIGURE 2 the device for generating the various control pulses required to establish the three discrete effective addresses will now be set forth. Depending upon whether the operation is to be a read into the memory or a read from the memory an original start read or start Write pulse is generated by the main control system (not shown) to the respective input of an Or circuit 401. The output of the Or circuit 461 on the line 4153 is employed to control the gating (not shown) necessary to permit the reading from the main memory of an original control address into the MAR. The output of the Or gate 401 is also introduced to the input or" a delay network, 405 of a type well-known in the art, which is so chosen that it will delay the input pulse a suiiicient length of time to permit the read out of the address designated by the MAR and its utilization. When the signal in delay 405 emerges tat the end of the delay interval, it is fed to a delay flop 467 via line 409. The delay flop produces an output on the line ill which is employed as the A signal for aiding in the generation of further effective addresses from the control address. The delay iiop will produce a steady signal level, once actuated for a length of time, as determined by its circuit parameters, and then return to an off condition. The duration of the A signal in this instance will be sufficient to permit a read out of the matrix of the data stored at the second effective address. The output from delay 405 is also fed over line 413 to a second delay network 415. This delay is proportioned to delay an output signal until the desired second read-out operation is completed. At the end of the delay period a signal will be read out on line 417 to a further delay fiop 4119. The output of delay fiop 419 produces a signal on line 421 which is employed as the B signal for aiding in the generation of the iinal effective address. The signal from the delay liop 419 will persist a sufficiently long time to permit read out from the matrix of the data stored at the third effective address.

While this invention has been described with reference to a particular form or size of matrix and a particular selected member of unique memory locations and addresses as well as a particular input code group, it should be understood that this procedure may be extended to include further and other configurations and basic codes without departing from the scope of this invention.

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

l. A translating device in which data having a first value pattern is translated into data having further unique and distinct value patterns in successive cycles of operation, one pattern being available during each operating cycle, comprising: a register means to receive and store said data having said a first value pattern and provided outputs indicative thereof; gating means selectively operable to translate said outputs indicative of said data having said first value pattern into outputs indicative of further unique and distinct value patterns, for each operating cycle of said gating means; means to selectively operate said gating means during each operating cycle and means to read out the resulting outputs having said further unique and distinct values each operating cycle.

2. A translating device in which data coded in a first system of notation is translated into data coded in a plurality of other systems Vof notation in successive cycles of operation, data in a different one of such other systems of notation being available at each operating cycle comprising: a register means to receive said data coded in a irst system of notation and provide outputs indicative of the value of the data stored; gating means connected to said register and selectively operable to translate said data coded in a first system of notation into data coded m another system of notation; means to selectively operate said gating means to provide data coded in a different of said other systems of notation for each operating cycle; means to provide successive operating cycles; means connecting said means to provide successive operating cycles to said means to selectively operate said gating means in order to fix the times at which said data coded in each of the different ones of said systems or" notation is available and means to read out and utilize said data in each of the different of said systems of notation as available.

3. A cyclic translating device in which data coded in a first system of notation is translated into a separate and distinct further system of notation in successive cycles of operation, and wherein data in one of said separate and distinct systems of notation is available at each operating cycle of the device comprising: a multisectional register means for accepting and storing a plurality of digits comprising bi-quinary coded decimal number and providing signals indicative of the values stored therein; first means connected to said register means for selectively translating the vaines stored therein into a plurality of unique binary numbers, one during each of three separate operating cycles; second means coupled to said first means to selectively control the operation of said first means during each of said operating cycles; means coupled to said second means to provide signals indicative of said three separate operating cycles; and read out means to permit utilization of each of said three separate binary numbers as they are formed.

4. A cyclic translating device in which data coded in a first system of notation is translated into a separate and distinct further system of notation for each operating cycle of the device comprising: a three section register means for accepting and storing the three digits of a biquinary coded decimal number and providing signals indicative of the values stored therein; first means connected to said register means for selectively translating the values stored therein into three unique binary numbers, one during each of three separate operating cycles; second means coupled to said lirst means to selectively control the operating of said iirst means during each of said operating cycles; means coupled to said second means to provide signals indicative of said three separate operating cycles; and read out means to permit utilization of each of said three separate binary numbers as they are formed.

5. A translating device in which data coded in a first system of notation is translated into further separate and distinct systems of notation during successive operating cycles comprising: a register means for accepting and storing data coded in said first system of notation; first means connected to said register means for selectively translating the values stored therein into three unique binary numbers, one during each of three separate operating cycles; first control means including gating means connected to said register means to produce outputs during a irst time period in accordance with the contents of said register means; second control means operative during a second time period to control said gating means and produce outputs in accordance with one of a further systems of notation; and means operative during a third time period to control said gating means and produce outputs in accordance with another of said further systems of notation; and means to utilize said data as available.

6. A translating device in which data coded in a first system of notation is translated into further separate and distinct systems of notation during successive operating cycles comprising: a register means for accepting and storing data coded in said first system of notation; gating means connected to said register means; first means operative during a first operating cycle to control said gating means according to the data stored in said register means to permit the contents of said register means to be gated unchanged if certain values are present in said register means, and to permit partial gating if other values are present in said register means;` second means coupled to said gating means to alter the signals gated during a second operating cycle to provide data coded in a second system of notation and third means coupled to said gating means and operative during a third operating cycle to provide data coded in a third system of notation.

7. A device as claimed in claim 6, wherein additional means are provided for inserting data at the outputs of said gating means when the contents of said register means is only partially gated.

8. A transiating device in which data coded in a rst system of notation is translated into further separate and distinct systems of notation during successive operating cycles comprising: a register' means for accepting and storing data coded in said first system of notation; gating means having output lines, said gating means being connected to said register means for receiving the output thereof; means operative during a first operating cycle to control said gating means according to the data stored in said register means to permit the contents of said register means to be gated unchanged if certci data is present in said register means and to permit partial gating if other data is present in said register means; first means to annessa CII insert data at tlie outputs of said gating means for any portion of data of the register means not gated; second means to insert data at the outputs of said gating means during a second operating cycle in accordance with the data originally stored by said register means to provide data coded in a second system of notation; third means to insert data at the outputs of said gating means during a third operating cycle in accordance with the data originally stored by said register means to provide data coded in a third system of notation; means to provide signals indicative of said three distinct operating cycles to said respective first, second and third means; and means to read out and utilize each of said three distinct data groups in their respective systems of notation.

References Cited in the file of this patent UNITED STATES PATENTS UNITED STATES PATENT OFFICE CERTIFICATE 0F CORRECTION Patent Noo 3 ,163 ,859 December 29 1964 Lloyd W. Stowe lt is herebg;r certified that error appears in the above numbered patent requiring correction and that the said Letters Patent should read as corrected below.

Column l0, in the title ofTable IIIc, for

[CH CU and CU =0] read [CH CU and CU =0] L+ l l L+ 2 I Signed and sealed this lst day of June l965.

(SEAL) Anest:

ERNEST W. SWIDER EDWARD J. BRENNER Attesting Officer Commissioner of Patents UNITED STATES PATENT OFFICE CERTIFICATE 0F CORRECTION Patent No. 3,163,859 December` 29, 1964 Lloyd W. Stowe It is hereby certified that error appears in the above numbered patent requiring correction and that the said Letters Patent should read as corrected below.

Column l0, in the title ofTable IIIC, for

[CH CU and CU =0] read [CH CU and CU :0] L 1 1 L+ 2 1 Signed and sealed this lst day of June 1965.

(SEAL) Attest:

ERNEST W. SWIDER EDWARD J. BRENNER Attesting Officer Commissioner of Patents 

8. A TRANSLATING DEVICE IN WHICH DATA CODED IN A FIRST SYSTEM OF NOTATION IS TRANSLATED INTO FURTHER SEPARATE AND DISTINCT SYSTEMS OF NOTATION DURING SUCCESSIVE OPERATING CYCLES COMPRISING: A REGISTER MEANS FOR ACCEPTING AND STORING DATA CODED IN SAID FIRST SYSTEM OF NOTION; GATING MEAN HAVING OUTPUT LINES, SAID GATING MEANS BEING CONNECTED TO SAID REGISTER MEANS FOR RECEIVING THE OUTPUT THEREOF; MEANS OPERATIVE DURING A FIRST OPERATING CYCLE TO CONTROL SAID GATING MEANS ACCORDING TO THE DATA STORED IN SAID REGISTER MEANS TO PERMIT THE CONTENTS OF SAID REGISTER MEANS TO BE GATED UNCHANGED IF CERTAIN DATA IS PRESENT IN SAID REGISTER MEANS AND TO PERMIT PARITIAL GATING IF OTHER DATA IS PRESENT IN SAID REGISTER MEANS; FIRST MEANS TO INSERT DATA AT THE OUTPUTS OF SAID GATING MEANS FOR ANY PORTION OF DATA OF THE REGISTER MEANS NOT GATED; SECOND MEANS TO INSERT DATA AT THE OUTPUTS OF SAID GATING MEANS DURING A SECOND OPERATING CYCLE IN ACCORDANCE WITH THE DATA ORIGINALLY STORED BY SAID REGISTER MEANS TO PROVIDE DATA CODED IN A SECOND SYSTEM OF NOTION; THIRD MEANS TO INSERT DATA AT THE OUTPUTS OF SAID GATING MEANS DURING A THIRD OPERATING CYCLE IN ACCORDANCE WITH THE DATA ORIGINALLY STORED BY SAID REGISTER MEANS TO PROVIDE DATA CODED IN A THIRD SYSTEM OF NOTATION; MEANS TO PROVIDE SIGNALS INDICATIVE OF SAID THREE DISTINCT OPERATING CYCLES TO SAID RESPECTIVE FIRST, SECOND AND THIRD MEANS; AND MEANS TO READ OUT AND UTILIZE EACH OF SAID THREE DISTINCT DATA GROUPS IN THEIR RESPECTIVE SYSTEMS OF NOTATION. 